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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.2 / dec. 2003 1 HY62KF16403E series 256kx16bit full cmos sram document title 256k x 16bit 2.7 ~ 3.6v super low power fcmos slow sram revision history revision no. history draft date remark 0.0 initial draft dec.26.2001 preliminary 0.1 absolute maximum ratings - vcc changed -0.3v to 4.6v -> -0.3v to 4.0v dc electric characteristics - icc changed 4ma -> 3ma - icc1 changed 25ma at 55ns -> 20ma at 55ns - icc1 changed 20ma at 70ns -> 15ma at 70ns - icc1 changed 3ma at 1us -> 2ma at 1us ac test conditions - output load changed 5pf -> 30pf data retention electric characteristics - iccdr changed 10ua -> 6ua marking information - part name changed hy62kf6403e -> HY62KF16403E nov.14.2002 final 0.2 add 44-pin padpitch to tsopii pa ckage information dec.26.2003 final
this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.2 / dec. 2003 2 HY62KF16403E series 256kx16bit full cmos sram description the HY62KF16403E is a high speed, super low power and 4m bit full cmos sram organized as 256k words by 16bits. the HY62KF16403E uses high performance full cmos process te chnology and is designed for high speed and low power circuit technology. it is particularly well-suited for the high density low power system application. this device has a data retent ion mode that guarantees data to remain valid at a minimu m power supply voltage of 1.2v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup - 1.2v(min) data retention standard pin configuration - 44pin 400mil tsop-ii (forward) 16m pseudo sram product family note 1) i : indust rial temperature. 2) current value is max. part number voltage speed operation current/icc standby current temp.( o c) sl ll HY62KF16403E-i 2.7~3.6 (v) 55/70 (ns) 3ma 6ua 15ua -40 ~ 85
rev 0.2 / dec. 2003 3 HY62KF16403E series 256kx16bit full cmos sram pin connection pad description symbol description cs chip select we write enable oe output enable lb lower byte control (io1~io8) ub upper byte control (io9~io16) i/o1 ~ i/o16 data inputs/outputs a0 ~ a17 address inputs v dd power(2.7v~3.6v) v ss ground nc no connection 1 12 13 22 44 33 32 23 a5 a6 a7 oe ub lb i/o16 i/o15 i/o13 vss vcc vcc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 a11 a12 a4 a3 a2 a1 a0 cs i/o3 i/o4 vss vcc i/o5 i/o6 i/o7 i/o8 we a15 a14 a13 i/o1 i/o2 a17 a16 tsopii (forward)
rev 0.2 / dec. 2003 4 HY62KF16403E series 256kx16bit full cmos sram functional block diagram 256k x 16bit super low power fcmos slow sram memory array 256k x 16 row decoder sense amp write driver data i/o buffer i/o1 i/o8 i/o9 i/o16 column decoder block decoder pre decoder add input buffer a0 a17 /cs /oe /lb /ub /we data i/o buffer a0 cs lb ub we
rev 0.2 / dec. 2003 5 HY62KF16403E series 256kx16bit full cmos sram ordering information note 1) i : industrial -40 ~ 85 o c absolute maximum rating 1) note1) stresses greater than those listed under absolute maxi mum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximu m rating conditions for extended period may affe ct reliability. truth table note 1). h=v ih , l=v il , x=don ' t care(v il or v ih ) 2). ub , lb (upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when lb is low, data is written or read to the lower byte, i/o1 - i/o8. when ub is low, data is written or read to the upper byte, i/o9 - i/o16. part number speed power temparature package HY62KF16403E-sd(i) 55/70 sl-part i 1) tsop-ii HY62KF16403E-dd(i) 55/70 ll-part i 1) tsop-ii parameter symbol rating unit input/output voltage v in , v out -0.3 to vcc+0.3v v power supply v dd -0.3 to 4.0 v ambient temperature t a -40 to 85 o c storage temperature t stg -55 to 150 o c power dissipation p d 1.0 w ball soldering temperature & time t solder 260 . 10 o c . sec mode cs we oe lb ub i/o power i/o1 ~ i/o8 i/o9 ~ i/o16 deselected h x x x x high-z high-z standby output disabled l x x h h high-z high-z active l h h x x high-z high-z read l h l lhd out high-z active hlhigh-z d out lld out d out write l l x lhd in high-z active hlhigh-z d in lld in d in
rev 0.2 / dec. 2003 6 HY62KF16403E series 256kx16bit full cmos sram dc operating condition (t a = -40 to 85 o c ) note : 1) vil=-1.5v for pulse width less then 30ns. undershoot is sampled, not 100% tested. dc characteristics (v dd = 2.7v ~ 3.6v, t a = -40 to 85 o c ) parameter symbol min typ max unit power supply voltage v dd 2.7 3.0 or 3.3 3.6 v gruond v ss 0 - 0v input high voltage v ih 2.2 - v cc+ 0.3 v input low voltage v il -0.3 1) - 0.6 v parameter symbol test condition speed unit min tpy. max input leakage current i li v ss v in v cc -1 1 ua output leakage current i lo v ss v out v cc cs =v ih or oe =v ih or we =v il -1 1 operating power supply current i cc cs =v il , v in =v ih or v il , i i/o =0ma -3 ma average operating current i cc 1 cs =v il , v in =v ih or v il , cycle time= min. 100% duty, i i/o =0ma 55ns 20 70ns 15 cs 0.2v, v in 0.2v or v cc -0.2v v in , cycle time=1us. 100% duty, i i/o =0ma -2 ttl standby current i sb cs =v ih , v in =v ih or v il - 300 ua standby current (cmos input) i sb1 v cc -0.2v cs, v cc -0.2v v in or v in v ss +0.2v 3.0 ~ 3.6 v -0.26 -0.215 2.7 ~ 3.3 v -0.26 -0.212 output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v
rev 0.2 / dec. 2003 7 HY62KF16403E series 256kx16bit full cmos sram ac operating test condition (t a = -40 to 85 o c ) ac test loads note 1) including jig and scope capacitance. capacitance (temp.= 25 o c, f=1.0mhz ) note : these parameters are sampled and not 100% tested. parameter value input pulse level 0.4 to 2.2v input rising and fall time 5ns input and output timing reference level 1.5v output load tclz, tolz, tchz, tohz, twhz , tow cl = 30pf + 1ttl load others cl = 30pf + 1ttl load parameter symbol condition max. unit input capacitance (add, cs , we , oe )c in v in = 0v 8 pf output capacitance (i/o) c out v i/o = 0v 10 pf d out 1728 ohm cl(1) 1029 ohm v tm =2.8v
rev 0.2 / dec. 2003 8 HY62KF16403E series 256kx16bit full cmos sram ac characteristics (ac operating conditions unless otherwise specified) parameter symbol 55ns 75ns unit min max min max read cycle read cycle time t rc 55 - 75 - ns address access time t aa -55-75 ns chip select access time t acs -55-75 ns output enable to output valid t oe -30-35 ns lb , ub access time t ba -55-75 ns chip select to output in low z t clz 10 - 10 - ns output enable to output in low z t olz 5-5- ns lb , ub enable to output in low z t blz 10 - 10 - ns chip disable to output in high z t chz 020025 ns out disable to output in high z t ohz 020025 ns lb , ub disable to output in high z t bhz 020025 ns output hold from address change t oh 10 - 10 - ns write cycle write cycle time t wc 55 - 75 - ns chip selection to end of write t cw 50 - 60 - ns address valid to end of write t aw 50 - 60 - ns lb , ub valid to end of write t bw 50 - 60 - ns address set-up time t as 0-0- ns write pulse width t wp 45 - 50 - ns write recovery time t wr 0-0- ns write to output in high z t whz 020020 ns data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0-0- ns output active from end of write t ow 5-5- ns
rev 0.2 / dec. 2003 9 HY62KF16403E series 256kx16bit full cmos sram read cycle 1 ( note 1, 4 ) read cycle 2 ( note 1, 2, 4 ) read cycle 3 ( note 1, 2, 4 ) add cs ub, lb oe data out high -z t rc t aa t acs t ba t oe t olz (3) t blz (3) t clz (3) t oh t chz (3) t bhz (3) t ohz (3) data valid add data out data valid t rc previous data t oh t aa t oh cs data out data valid t clz (3) t acs t chz (3) ub, lb
rev 0.2 / dec. 2003 10 HY62KF16403E series 256kx16bit full cmos sram notes : 1. a read occurs during the overlap of a low oe , a high we , a low cs and ub and /or lb . 2. oe = v il 3. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. cs in high for the standby, low for active. ub and lb in high for the standby, low for active.
rev 0.2 / dec. 2003 11 HY62KF16403E series 256kx16bit full cmos sram write cycle 1 ( note 1, 4, 8 ) ( we controlled ) write cycle 2 ( note 1, 4, 8 ) ( cs controlled ) add cs ub, lb we data out data in t wc t cw t bw t wp t wr (2) data valid t aw t as high -z t dw t dh t whz (3,7) t ow (5) (6) add cs ub, lb we data out data in t wc t cw t bw t wp t wr (2) data valid t aw high-z t dw t dh high-z t as
rev 0.2 / dec. 2003 12 HY62KF16403E series 256kx16bit full cmos sram notes : 1. a write occurs during the overlap of a low we , a low cs and a low ub and/or lb . 2. twr is measured from the earlier of cs , lb , ub, or we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output mu st not be applied. 4. if the cs , lb and ub low transition occur simultaneously with the we low transition or after the we transition, outputs remain in a high impedance state. 5. q(data out) is the invalid data. 6. q(data out) is the read data of the next address. 7. cs in high for the standby, low for active ub and lb in high for the standby, low for active. data retention electric characteristic (t a = -40 to 85 o c ) notes : 1. typical values are under the condition of ta = 25 o c . 2. typical value are sampled and not 100% tested. data retention timing diagram symbol parameter test condition min typ. 1) max unit v dr vcc for data retention v cc -0.2v cs, v cc -0.2v v in or v in v ss +0.2v 1.2 - 3.6 v i ccdr data retention current v cc=1.5v v cc -0.2v cs or v cc -0.2v v in or v in v ss +0.2v sl - 0.1 3.0 ua ll - 0.1 6.0 t cdr chip deselect to data retention time see data retention timing diagram 0-- ns t r operating recovery time trc - - cs vdr cs > v cc -0.2v t cdr t r vss vcc 2.7v vih data retention mode
rev 0.2 / dec. 2003 13 HY62KF16403E series 256kx16bit full cmos sram package information 44pin 400mil thin small ou tline package forward (d) 0.4700 (11.938) 0.4620 (11.735) 0.729(18.517) 0.4040 (10.262) 0.3960 (10.058) 0.4040 (10.262) 5deg 0deg 0.0235 (0.597) 0.0160 (0.406) 0.0083 (0.210) 0.0047 (0.120) 0.0235 (0.597) 0.0160 (0.406) 0.0083 (0.210) 0.0047 (0.120) 0.0315 (0.80) 0.047 (1.194) 0.039 (0.991) 0.0059 (0.150) 0.002 (0.050) 0.016 (0.4) 0.0320 (0.805) 0.012 (0.3) unit : inch (mm) max min (bsc) (bsc)

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